1. Field of the Invention
The present invention relates to the delay lock loop (DLL) circuit in a double data rate (DDR) synchronous dynamic random access memory (SDRAM), and more particularly to the shift register portion of the DLL circuit.
2. State of the Art
In a synchronous dynamic random access memory (SDRAM) system, operations performed within the system, such as read or write operations, are clocked or synchronized to the rising and falling edge of an external system clock. In particular, in a double data rate (DDR) SDRAM system or device, data is clocked out of the device such that it is synchronized with both the rising and falling edge of the external clock. In order to implement this type of synchronization, a delay lock loop (DLL) circuit is used.
FIG. 1A shows a system block diagram of a SDRAM 10 design including DLL circuitry 11 which in response to external clock 11A provides an optimum delayed clock signal 11B to the data output buffer 12 such that the data 12A from the DRAM core 13 is output from the buffer 12 on the rising and falling edge of the external clock 11A to provide Output Data signal 12B.
FIG. 1B shows a basic prior art digital DLL circuit 14 including an input receiver buffer 15 for receiving an external clock signal 15A and providing an internal clock signal 15B to a delay unit circuit 16. The delay unit circuit 16 is programmably adjustable by a digital state stored within a shift register 17 to provide a variable time delay so as to generate a clock signal 16A that corresponds to the internal clock signal 15B delayed by the amount established within the delay unit circuit. Clock signal 16A is used to clock output buffer 18 such that data from the DRAM core 18A is clocked through buffer 18 on the subsequent rising and falling edges of the external clock signal 16A. The DLL circuit further includes a feedback loop having a Phase Detector 19 which, depending on the phase difference between a feedback clock signal 16A' and the internal clock signal 15B causes the shift register to shift left or right thereby increasing or decreasing, respectively, the delay value stored within shift register 17. Dummy output buffer 20 and Dummy receiver buffer 21 provide a path for feedback Clk signal 16A that is the equivalent to the path for the external clock signal 15A. The delay value stored in register 17 is used to program delay unit circuit 16 such that data 18A is clocked through buffer 18 to the output of the memory device on each of the next rising or falling edge of the external clock signal.
FIG. 1C shows a typical prior art bi-directional shift register usable in the DLL circuit shown in FIG. 1B. The shift register includes a plurality of clocked D-type flip-flops (FF1, FF2 . . . FF(n)) and a plurality of multiplexers (MUX1, MUX2 . . . MUX(n))--one coupled to the input of each latch. Each multiplexer passes data from the output of either the previous or next flip-flop within the shift register to the input of its corresponding flip-flop to perform either the right or left shift operation. The multiplexers pass the data dependent on the right and left shift control signals provided by the phase detector and coupled to the select input port (S) of each multiplexer in FIG. 1C. The flip-flop is generally edge triggered by the clock signal (CLK) such that on a first clock cycle edge (either rising or falling), the next or previous data passed by the multiplexer is clocked into the flip-flop and on the second clock cycle edge (the same edge as the first cycle) the data is latched to the flip-flop output.
FIG. 1D shows a one prior art design of a D type flip-flop typically used within the shift register shown in FIG. 1C. The flip-flop is designed with two J-K edge-triggered flip flop latching stages--a master latch and a slave latch. As is well known in digital circuit design, latches are typically implemented with cross-coupled NAND gate circuits as shown in FIG. 1D.
One problem which is encountered when designing a conventional DLL circuit using the shift register as shown in FIG. 1C implemented with the flip-flop as shown in FIG. 1D is that in order to cover a wide operating frequency range while maintaining an acceptable adjustment resolution a large number of individual delay unit elements and an equal number of flip-flops are required within the DLL circuit design. However, increasing the number of delay unit elements and flip-flops increases circuit complexity, size, and power consumption. Moreover, increased complexity, size, and power consumption results in an increase in noise inducement within the DLL circuit during operation and undesirable affects due to noise. For instance, jitter (i.e., signal shifting over time) within the DLL circuit strongly depends on noise coupling within the DLL circuit. Hence, a significant design consideration when designing a DLL circuit is the simplification of the shift register design within the DLL circuit.
What would be desirable is to reduce the complexity of the bi-directional shift register used within a DLL circuit so as to minimize circuit noise and silicon space consumption of the bi-directional shift register. Reducing shift register complexity also allows a more robust delay unit and shift register to be designed into the DLL circuit which can provide increased resolution and reliability.